As a means for restoring data retained in a register such as a flip-flop after the power cutoff, for example, a data retention control circuit may use a ferroelectric device.
FIG. 5 is a view schematically illustrating a conventional data retention control circuit 30. The data retention control circuit 30 includes a controller 13a and a data retention circuit 13b. 
The controller 13a transmits a control signal SDS11, a control signal SKS11, a control signal SKS12, a control signal SK11, and a control signal SK12 to the data retention circuit 13b. 
The data retention circuit 13b includes a data retention part M11, a transmission control part DS11, a ferroelectric storage part K11, a ferroelectric control part KS11, and a sense amplifier SA11.
The data retention part M11 includes a transistor Nc11, a logic circuit NAND11, and a logic circuit NAND12.
The transistor Nc11 transmits a data signal Din11 input from an input terminal DTin11 to the logic circuit NAND11, for example, at a rising timing of a clock signal CLK11 which is output from the controller 13a and input through an input terminal Tc1k11 to a gate terminal G.
The logic circuit NAND11 inverts a logic level of the data signal Din11 into a logic signal Nout11 to be output. The logic circuit NAND12 inverts the output signal Nout11 into a logic signal Nout12 to be output.
The data retention part M11 circulates the output logic signals Nout11 and Nout12 between the logic circuit NAND11 and the logic signal NAND12 to retain a logic level based on the data signal Din11, and an inverter INV11 inverts the logic signal Nout11 to output an output signal Dout11 through an output terminal DTout11.
The transmission control part DS11 includes a logic circuit NOR11 and a logic circuit NOR12. Transmission of the logic signal Nout11 by the logic circuit NOR11 and transmission of the logic signal Nout12 by the logic circuit NOR12 are controlled by the control signal SDS11, which is output from the controller 13a. 
The ferroelectric storage part K11 includes a ferroelectric device C11 and a ferroelectric device C12.
The ferroelectric device C11 has an anode terminal, which is connected to the controller 13a, and a cathode terminal, which is connected to an output terminal of the logic circuit NOR11. The ferroelectric device C11 retains a logic level of the logic signal Nout11 as storage data KD11. Here, a connection point between the cathode terminal of the ferroelectric device C11 and the logic circuit NOR11 will be referred to as Nd11.
The ferroelectric device C12 has an anode terminal, which is connected to the controller 13a, and a cathode terminal, which is connected to an output terminal of the logic circuit NOR12. The ferroelectric device C12 retains a logic level of the logic signal Nout12 as storage data KD12. Here, a connection point between the cathode terminal of the ferroelectric device C12 and the logic circuit NOR12 will be referred to as Nd12.
The ferroelectric control part KS11 includes a transistor N11 and a transistor N12.
The transistor N11 has a gate terminal G connected to the controller 13a to receive the control signal SKS11, and a drain terminal D connected to a node Nd13. The node Nd13 is closer to the output terminal of the logic circuit NOR11 than the node Nd11 is, which is the connection point between the logic circuit NOR11 and the cathode terminal of the ferroelectric device C11. The transistor N11 further has a source terminal S connected to the controller 13a and the anode terminal of the ferroelectric device C11. The transistor N11 is turned on and off by the control signal SKS11 to thereby control whether to short both ends of the ferroelectric device C11.
The transistor N12 has a gate terminal G connected to the controller 13a to receive the control signal SKS12, and a drain terminal D connected to a node Nd14. The node Nd14 is closer to the output terminal of the logic circuit NOR12 than the node Nd12 is, which is the connection point between the logic circuit NOR12 and one end of the ferroelectric device C12. The transistor N12 further has a source terminal S connected to the anode terminal of the ferroelectric device C12. The transistor N12 is turned on and off by the control signal SKS12 to thereby control whether to short both ends of the ferroelectric device C12.
The sense amplifier SA11 is driven by a control signal SSA11 which is output from the controller 13a. The sense amplifier SA11 has an input terminal SAin11 to which the storage data KD11 which is retained in the ferroelectric device C11 is input, and an input terminal SAin12 to which the storage data KD12 retained in the ferroelectric device C12 is input. When the control signal SSA11 has a high level, the sense amplifier SA11 compares the storage data KD11, which is input to the input terminal SAin11, and the storage data KD12, which is input to the input terminal SAin12. When the storage data KD11 has a higher level than the storage data KD12, the sense amplifier SA11 supplies an output signal SSAout11 having a high level to the logic circuit NAND12 and supplies an output signal SAout12 having a low level to the logic circuit NAND11. Further, when the storage data KD11 has a lower level than the storage data KD12 has, the sense amplifier SA11 supplies an output signal SSAout11 having a low level to the logic circuit NAND12 and supplies an output signal SAout12 having a high level to the logic circuit NAND11.
A normal operation in the data retention control circuit 30 illustrated in FIG. 5, that is, an operation of retaining the data signal Din11 in the data retention part M11 and outputting it as an output signal Dout11 is performed in a state where an electrical connection between the data retention part M11 and the ferroelectric storage part K11 is blocked by the control signal SDS11 having a low level.
Characteristics of the ferroelectric device C11 of the ferroelectric storage part K11 in the data retention control circuit 30 illustrated in FIG. 5 are tested under the condition where transmission of the logic signal Nout11 to the ferroelectric device C11 and transmission of the logic signal Nout12 to the ferroelectric device C12 are blocked by the control signal SDS11 with a low level. For example, to test characteristics of the ferroelectric device C11, when the transistor N11 is turned off by the control signal SKS11 with a low level and the transistor N12 is turned on by the control signal SKS12 with a high level, a test voltage having a predetermined voltage level is output from the controller 13a as the control signal SK12. In this case, the storage data KD11 of the ferroelectric device C11 is input to the input terminal SAin11 of the sense amplifier SA11, and the control signal SKS12 is output from the controller 13a and input to the input terminal SAin12 through the transistor N12. Based on a comparison between the control signal SKS12 and the storage data KD11, the sense amplifier SA11 outputs the output signal SSAout11 to the logic circuit NAND12 while outputting the output signal SAout12 to the logic circuit NAND11. Further, by detecting changes in the output signal Dout11 which are obtained by gradually changing a test voltage Vt11, a voltage level of the storage data KD11 stored in the ferroelectric device C11 is detected for the test of the characteristics of the ferroelectric device C11. Also, characteristics of the ferroelectric device C12 may be tested in the same manner.
In the characteristics test of the ferroelectric device C11 of the conventional data retention control circuit 30, since the control signal SK12 is input to the input terminal SAin12 via the transistor N12, a potential difference occurs between the control signal SK12, which is directly applied to the anode terminal of the ferroelectric device C12 from the controller 13a, and the control signal SKS12, which is applied to the cathode terminal of the ferroelectric device C12 via the transistor N12, due to ON resistance of the transistor N12. This causes concern that unintended data may be recorded in the ferroelectric device C12.
In the characteristics test of the ferroelectric device C12, the storage data KD12 which is unintentionally recorded in the ferroelectric device C12 affects a voltage level of the control signal SK12, which is input to the input terminal SAin12 of the sense amplifier SA11 and, causes a problem that the precision of the characteristics test of the ferroelectric device C12 is degraded. This problem may arise in regard to the ferroelectric device C11 as well.